The present invention relates generally to repeaters used in computer networks. Specifically, the invention relates to semiconductor integration of a plurality of transceiver ports with repeater functionality while retaining a port expansion capability for the integrated repeater.
U.S. Pat. No. 5,265,123 hereby expressly incorporated by reference for all purposes, provides an effective solution to port expansion capability for repeaters, particularly for integrated repeaters. FIG. 1 is a block schematic diagram of a repeater 10 implemented according to an embodiment of U.S. Pat. No. 5,265,123.
Repeater 10 includes three Integrated Multi-port Repeaters (IMR) 12.sub.i coupled together to form the single repeater 10. Details regarding making and using repeater 10 are included in the incorporated U.S. Pat. No. 5,265,123 and will not be further described herein. An important aspect of the coupling of the IMRs 12 is that they collectively operate together so as to form a single synchronized repeater. As noted, repeater 10 has three times the number of data ports as a single IMR 12, thereby providing a coupling that effectively expands the number of ports of a single IMR 12.
An expansion port function of each IMR 12 includes an output request (REQ) signal, an input acknowledge (ACK) signal, an input collision (COL) signal, a bidirectional data (DAT) signal and a bidirectional JAM signal. An expansion bus 14 intercouples the individual IMRs 12 making repeater 10. Expansion bus 14 includes the DAT and JAM signals. In one preferred embodiment of U.S. Pat. No. 5,265,123, repeater 10 includes an arbiter module 16 that facilitates expansion bus 14 contention resolution and helps to synchronize collision state machines included in an IMR 12 upon detection of a collision. Arbiter 16 detects collision conditions by sensing multiple requests for access to expansion bus 14. Detection of a collision condition results in arbiter 16 asserting the COL signal to each IMR 12.
Repeater 12 is an effective solution to port expandability of integrated repeater semiconductor devices. A need is developing, however, for very low cost solutions to the problem of repeater port expandability. A solution such as shown in FIG. 1 is not a lowest cost solution due to the use of the external arbiter.
FIG. 2 is an alternate preferred embodiment from U.S. Pat. No. 5,265,123 that includes a repeater 20 that includes three IMRs 22. IMRs 22 are daisy-chained together to provide a single repeater. Each IMR 22 includes an internal arbiter function. Each IMR 22 includes a LINK IN port, a LINK OUT port, a COL port and a DAT port. Any particular IMR 22 will assert LINK OUT as long as LINK IN is asserted and no port on the particular IMR 22 is asserted. Each IMR 22 will assert the COL signal when multiple ports on a single IMR 22 are receiving OR when a single port is receiving and LINK IN is not asserted. Additional details regarding operation of repeater 20 are provided in U.S. Pat. No. 5,265,123.
While the implementation shown in FIG. 2 is a lower cost solution, propagation delays through the daisy-chained IMRs 22 effectively limits the degree of expandability of repeater 20.